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X88257 8051 Microcontroller Family Compatible 256K
X88257
E2 Micro-Peripheral
DESCRIPTION
32,768 x 8 Bit
FEATURES * Multiplexed Address/Data Bus --Direct Interface to Popular 8051 Family * High Performance CMOS --Fast Access Time, 120ns --Low Power --60mA Active Maximum --500A Standby Maximum * Software Data Protection * Toggle Bit Polling --Early End of Write Detection * Page Mode Write --Allows up to 128 Bytes to be Written in One Write Cycle * High Reliability --Endurance: 10,000 Write Cycle --Data Retention: 100 Years * 28-Lead PDIP Package * 28-Lead SOIC Package * 32-Lead PLCC Package
The X88257 is an 32K x 8 E2PROM fabricated with advanced CMOS Textured Poly Floating Gate Technology. The X88257 features a multiplexed address and data bus allowing direct interface to a variety of popular single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface circuitry.
FUNCTIONAL DIAGRAM
CE, CE WR RD PSEN A8-A14 CONTROL LOGIC X D E C O D E SOFTWARE DATA PROTECT
ALE
L A T C H E S
32K x 8 E2PROM
Y DECODE I/O & ADDRESS LATCHES AND BUFFERS A/D0-A/D7
6509 ILL F02.1
(c) Xicor, Inc. 1994-1997 Patents Pending 6509-1.9 4/9/96 T2/C5/D8 NS
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Characteristics subject to change without notice
X88257
PIN DESCRIPTIONS Address/Data (A/D0-A/D7) Multiplexed low-order addresses and data. The addresses flow into the device while ALE is HIGH. After ALE transitions from a HIGH to LOW the addresses are latched. Once the addresses are latched these pins input data or output data depending on RD, WR, PSEN, and CE. Addresses (A8-A14) High order addresses flow into the device when ALE = VIH and are latched when ALE goes LOW. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, ALE is LOW, and CE is LOW, the X88257 is placed in the low power standby mode. If CE is used to select the device, the CE must be tied LOW. Chip Enable (CE) Chip enable is active HIGH. When CE is used to select the device, the CE must be tied HIGH. Program Store Enable (PSEN) When the X88257 is to be used in a 8051-based system, PSEN is tied directly to the microcontroller's PSEN output. Read (RD) When the X88257 is to be used in a 8051-based system, RD is tied directly to the microcontroller's RD output. Write (WR) When the X88257 is to be used in a 8051-based system, WR is tied directly to the microcontroller's WR output. Address Latch Enable (ALE) Addresses flow through the latches to address decoders when ALE is HIGH and are latched when ALE transitions from a HIGH to LOW. PIN NAMES Symbol ALE A/D0-A/D7 A8-A14 RD WR PSEN CE, CE VSS VCC NC
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PSEN CE NC NC NC NC NC NC A/D0 5 6 7 8 9 10 11 12 X88257
A14 A12 ALE PSEN CE NC NC NC NC NC A/D0 A/D1 A/D2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PIN CONFIGURATION
PDIP SOIC 28 27 26 25 24 23 X88257 22 21 20 19 18 17 16 15 VCC WR A13 A8 A9 A11 RD A10 CE A/D7 A/D6 A/D5 A/D4 A/D3
6509 FHD F01.3
PLCC
ALE VCC A12 A14 NC WR A13
4
3
2
1 32 31 30 29 28 27 26 25 24 23 22
A8 A9 A11 NC RD A10 CE A/D7 A/D6
13 21 14 15 16 17 18 19 20
A/D1 A/D2 VSS A/D3 A/D4 A/D5 NC
6509 FHD F01A.5
Description Address Latch Enable Address Inputs/Data I/O Address Inputs Read Input Write Input Program Store Enable Input Chip Enable Ground Supply Voltage No Connect
6509 PGM T01.1
X88257
TYPICAL APPLICATION
U? 31 19 EA/VP X1 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE/P TXD RXD 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 11 12 12 15 16 17 18 19 A/D0 A/D1 A/D2 A/D3 A/D4 A/D5 A/D6 A/D7
18 9
X2 RESET
12 13 14 15 1 2 3 4 5 6 7 8
INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 8051
25 A8 24 A9 21 A10 23 A11 2 A12 26 A13 1 A14 20 CE CE 22 RD 27 WR 4 PSEN 3 ALE X88257
6509 ILL F03.3
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PRINCIPLES OF OPERATION The X88257 is a highly integrated peripheral device for a wide variety of single-chip microcontrollers. The X88257 provides 32K-bytes of 5V E2PROM which can be used either for program storage, data storage or a combination of both, in systems based upon Harvard (80XX) architectures. The X88257 incorporates the interface circuitry normally needed to decode the control signals and demultiplex the address/data bus to provide a "seamless" interface. The interface inputs on the X88257 are configured such that it is possible to directly connect them to the proper interface signals of the appropriate single-chip microcontroller. In the Harvard type system, the reading of data from the chip is controlled either by the PSEN or the RD signal, which essentially maps the X88257 into both the Program and the Data Memory address map. The X88257 also features the industry standard 5V E2PROM characteristics such as byte or page mode write and Toggle Bit Polling.
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DEVICE OPERATION Modes--Mixed Program/Data Memory By properly assigning the address spaces, a single X88257 can be used as both the program and data memory. This would be accomplished by connecting all the 8051 control outputs to the corresponding inputs of the X88257. Program Memory Mode This mode of operation is read-only. The PSEN and ALE inputs of the X88257 are tied directly to the PSEN and ALE outputs of the microcontroller. The RD and WR inputs are tied HIGH. When ALE is HIGH, the A/D0-A/D7 and A8-A14 addresses flow into the device. The addresses, both lowand high-order, are latched when ALE transitions LOW (VIL). PSEN will then go LOW and after tPLDV; Valid data is presented on the A/D0-A/D7 pins. CE must be LOW during the entire operation.
X88257
DATA MEMORY MODE This mode of operation allows both read and write functions. The PSEN input is tied to VIH or to VCC through a pull-up resistor. The ALE, RD, and WR inputs are tied directly to the microcontroller ALE, RD, and WR outputs. Read This operation is quite similar to the program memory read. A HIGH to LOW transition on ALE latches the addresses and the data will be output on the AD pins after RD goes LOW (tRLDV). Write A write is performed by latching the addresses on the falling edge of ALE. Then WR is strobed LOW followed by valid data being presented at the A/D0-A/D7 pins. The data will be latched into the X88257 on the rising edge of WR. To write to the X88257, a three-byte command sequence must precede the byte(s) being written. (See Software Data Protection.)
MODE SELECTION CE VCC HIGH LOW LOW LOW PSEN X X LOW HIGH HIGH RD X X HIGH LOW HIGH WR X X HIGH HIGH Mode Standby Standby Read Read Write I/O High Z High Z DOUT DOUT DIN Power Standby (CMOS) Standby (TTL) Active Active Active
6509 PGM T02
PAGE WRITE OPERATION Regardless of the microcontroller employed, the X88257 supports page mode write operations. This allows the microcontroller to write from 1 to 128 bytes of data to the X88257. Each individual write within a page write operation must conform to the byte write timing requirements.
The falling edge of WR starts a timer delaying the internal programming cycle 100s. Therefore, each successive write operation must begin within 100s of the last byte written. The following waveforms illustrate the sequence and timing requirements.
Page Write Timing Sequence for WR Controlled Operation
OPERATION BYTE 0 BYTE 1 BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR NEXT WRITE OPERATION
CE
ALE
A/D0-A/D7
AIN
DIN
AIN
DIN
AIN
DIN
AIN
DIN
AIN
DOUT
AIN
AIN
A8-A14
An
An
An
An
An
ADDR
Next Address
WR
PSEN(RD) tBLC tWC
6509 ILL F08.1
Notes: (1) For each successive write within a page write cycle A7-A14 must be the same.
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X88257
TOGGLE BIT POLLING Because the typical write timing is less than the specified 5ms, Toggle Bit Polling has been provided to determine the early end of write. During the internal programming cycle I/O6 will toggle from "1" to "0" and "0" to "1" on Toggle Bit Polling RD/WR Control
OPERATION LAST BYTE WRITTEN I/O6=X I/O6=X I/O6=X I/O6=X X88C64 READY FOR NEXT OPERATION
subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.
CE
ALE
A/D0-A/D7
AIN
DIN
AIN
DOUT
AIN DOUT
AIN DOUT
AIN
DOUT
AIN
A8-A14
An
An
An
An
An
ADDR
WR
RD
6509 ILL F09.1
SOFTWARE DATA PROTECTION Software Data Protection (SDP) is employed to protect the entire array against inadvertent writes. To write to the X88257, a three-byte command sequence must precede the byte(s) being written. All write operations, both the command sequence and any data write operations must conform to the page write timing requirements.
Writing with SDP
WRITE AA TO 5555
WRITE 55 TO 2AAA
WRITE A0 TO 5555
PERFORM BYTE OR PAGE WRITE OPERATIONS
WAIT tWC
EXIT ROUTINE
6509 ILL F10.1
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X88257
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. -65C to +135C Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to VSS .................................. -1V to +7V D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. 300C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military Min. 0C -40C -55C Max. +70C +85C +125C
6509 PGM T03.1
Supply Voltage X88257
Limits 5V 10%
6509 PGM T04.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol ICC ISB1(CMOS) Parameter VCC Current (Active) VCC Current (Standby) Min. Max. 60 500 Units mA A Test Conditions CE = RD = VIL, All I/O's = Open,Other Inputs = VCC CE = VCC - 0.3V, All I/O's = Open,Other Inputs = VCC - 0.3V, ALE = VIL CE = VIH, All I/O's = Open, Other Inputs = VIH, ALE = VIL VIN = VSS to VCC VOUT = VSS to VCC, RD = VIH = PSEN
ISB2(TTL) ILI ILO VlL(3) VIH(3) VOL VOH
VCC Current (Standby) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage -1 2 2.4
6 10 10 0.8 VCC + 0.5 0.4
mA A A V V V V
IOL = 2.1mA IOH = -400A
6509 PGM T05.1
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V Symbol CI/O(4) CIN(4) POWER-UP TIMING Symbol tPUR(4) tPUW(4) Parameter Power-Up to Read Power-Up to Write Max. 1 5 Units ms ms
6509 PGM T07
Test Input/Output Capacitance Input Capacitance
Max. 10 6
Units pF pF
Conditions VI/O = 0V VIN = 0V
6509 PGM T06
Notes: (3) VIL min. and VIH max. are for reference only and are not tested. (4) This parameter is periodically sampled and not 100% tested.
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X88257
A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 0V to 3V 10ns 1.5V
6509 PGM T08.1
EQUIVALENT A.C. TEST CIRCUIT
5V 1.92K OUTPUT 1.37K 100pF
6509 ILL F04.3
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) PSEN Controlled Read Cycle Symbol tLHLL tAVLL tLLAX tPLDV tPHDX tELLL PWPL tPS tPH tPHDZ (5) tPLDX (5) Parameter ALE Pulse Width Address Setup Time Address Hold Time PSEN Read Access Time Data Hold Time Chip Enable Setup Time PSEN Pulse Width PSEN Setup Time PSEN Hold Time PSEN Disable to Output in High Z PSEN to Output in Low Z Min. 80 20 30 120 0 7 150 30 20 50 10 Max. Units ns ns ns ns ns ns ns ns ns ns ns
6509 PGM T09
PSEN Controlled Read Timing Diagram
tPH CE tLHLL ALE tAVLL A/D0-A/D7 AIN tPLDX tPLDV A8-A14 tPS PSEN
6509 ILL F05.1
tELLL
tPH
tLLAX DOUT tPHDX tPHDZ ADDRESS PWPL
Note:
(5) This parameter is periodically sampled and not 100% tested.
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X88257
RD Controlled Read Cycle Symbol tLHLL tAVLL tLLAX tRLDV tRHDX tELLL PWRL tRDS tRDH tRHDZ (6) tRLDX (6) Parameter ALE Pulse Width Address Setup Time Address Hold Time RD Read Access Time Data Hold Time Chip Enable Setup Time RD Pulse Width RD Setup Time RD Hold Time RD Disable to Output in High Z RD to Output in Low Z Min. 80 20 30 120 0 7 150 30 20 50 0 Max. Units ns ns ns ns ns ns ns ns ns ns ns
6509 PGM T10
RD Controlled Read Timing Diagram
tRDH CE tLHLL ALE tAVLL A/D0-A/D7 AIN tRLDX tRLDV A8-A14 tRDS RD
6509 ILL F06.1
tELLL
tRDH
tLLAX DOUT tRHDX tRHDZ ADDRESS PWRL
Note:
(6) This parameter is periodically sampled and not 100% tested.
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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X88257
WR Controlled Write Cycle Symbol tLHLL tAVLL tLLAX tDVWH tWHDX tELLL tWLWH tWRS tWRH tBLC tWC (7) Parameter ALE Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Chip Enable Setup Time WR Pulse Width WR Setup Time WR Hold Time Byte Load Time (Page Write) Write Cycle Time Min. 80 20 30 50 30 7 120 30 20 0.5 Max. Units ns ns ns ns ns ns ns ns ns s ms
6509 PGM T11
100 5
WR Controlled Write Timing Diagram
tWRH CE tLHLL ALE tAVLL A/D0-A/D7 AIN tLLAX DIN tDVWH A8-A14 tWRS WR
6509 ILL F07.1
tELLL
tWRH
tWHDX ADDRESS
tWLWH
Note:
(7) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation.
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X88257
NOTES
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X88257
NOTES
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X88257
PACKAGING INFORMATION
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.470 (37.34) 1.400 (35.56)
0.557 (14.15) 0.510 (12.95) PIN 1 INDEX PIN 1 1.300 (33.02) REF. 0.085 (2.16) 0.040 (1.02)
SEATING PLANE 0.160 (4.06) 0.120 (3.05)
0.160 (4.06) 0.125 (3.17)
0.030 (0.76) 0.015 (0.38)
0.110 (2.79) 0.090 (2.29)
0.065 (1.65) 0.040 (1.02)
0.022 (0.56) 0.014 (0.36)
0.625 (15.88) 0.590 (14.99)
TYP. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F04
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X88257
PACKAGING INFORMATION
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.299 (7.59) 0.290 (7.37)
0.419 (10.64) 0.394 (10.01)
0.020 (0.508) 0.014 (0.356)
0.713 (18.11) 0.697 (17.70)
0.105 (2.67) 0.092 (2.34)
BASE PLANE SEATING PLANE 0.050 (1.270) BSC 0.012 (0.30) 0.003 (0.08)
0.050" TYPICAL 0.0200 (0.5080) X 45 0.0100 (0.2540) 0.013 (0.32) 0.008 (0.20) 0.050" TYPICAL 0.42" MAX
0 - 8
0.0350 (0.8890) 0.0160 (0.4064)
FOOTPRINT
0.030" TYPICAL 28 PLACES
NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3926 FHD F17
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X88257
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.420 (10.67)
0.050" TYPICAL
0.030" TYPICAL 32 PLACES
0.510" TYPICAL
0.050" TYPICAL
0.400"
0.050 (1.27) TYP.
FOOTPRINT
0.300" REF 0.410"
0.045 (1.14) x 45
0.021 (0.53) 0.013 (0.33) TYP. 0.017 (0.43)
0.495 (12.57) 0.485 (12.32) TYP. 0.490 (12.45) 0.453 (11.51) 0.447 (11.35) TYP. 0.450 (11.43) 0.300 (7.62) REF. PIN 1
SEATING PLANE 0.004 LEAD CO - PLANARITY -- 0.015 (0.38) 0.095 (2.41) 0.060 (1.52) 0.140 (3.56) 0.100 (2.45) TYP. 0.136 (3.45) 0.048 (1.22) 0.042 (1.07)
0.595 (15.11) 0.585 (14.86) TYP. 0.590 (14.99) 0.553 (14.05) 0.547 (13.89) TYP. 0.550 (13.97) 0.400 (10.16)REF. 3 TYP.
NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
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X88257
ORDERING INFORMATION
X88257 Device
X
X Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C M = Military = -55C to +125C Package P = 28-Lead Plastic DIP S = 28-Lead SOIC J = 32-Lead PLCC
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness.
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